1. Field of the Invention
Embodiments of the invention relate to frequency synthesizer circuits, and more particularly to adjustment of the phases of I and Q signals produced by frequency synthesizer circuits.
2. Related Technology
Frequency synthesizer circuits are widely used to generate local oscillator signals in radio frequency (RF) transmitter and receiver devices. Frequency synthesizers are typically implemented as phase locked loops. FIG. 1 shows an example of a conventional phase locked loop frequency synthesizer. The primary frequency generating element of the phase locked loop is a voltage controlled oscillator 10 that produces an output frequency corresponding to a charge stored in a low pass filter 12. The charge in the low pass filter 12 is controlled by a charge pump 14 that drives current into or out of the low pass filter 12 in response to a control signal provided by a phase frequency detector 16. The phase frequency detector 16 produces the control signal based on comparison of a signal representing the frequency of the voltage controlled oscillator to a signal representing a reference frequency. The signal representing the reference frequency is generated by dividing the signal from a reference frequency generator 18 such as a crystal oscillator using a frequency divider 20. The signal representing the frequency of the voltage controlled oscillator 10 is also divided by a frequency divider 22 so that the frequencies compared by the phase frequency detector 16 are approximately the same when the voltage controlled oscillator 10 is producing the desired frequency.
It is often necessary for the frequency synthesizer to generate both in-phase (I) and quadrature (Q) signals. To do so, the frequency synthesizer typically employs a frequency divider 24 that divides the output of the voltage controlled oscillator 10 by a factor of four. This produces a 0 degree output signal having a frequency that is one-quarter the frequency of the VCO 10, and additional signals at the same frequency with edges at 90 degrees, 180 degrees, and 270 degrees with respect to the 0 degree output signal. The 0 degree and 180 degrees signals constitute a differential in-phase signal pair, and the 90 degree and 270 degree signals constitute a differential quadrature signal pair.
Present generation RF devices such as wireless LAN transceivers operate at a very high frequencies and require very high local oscillator frequencies. For example, wireless LAN transceivers that support the 801.11 b/g standards must be capable of modulating and demodulating signals in the range of 2.412 GHz to 2.84 GHz, and transceivers that support the 802.11 a/j standards must be capable of modulating and demodulating signals in the range of 4.912 GHz to 5.805 GHz, At these frequencies, propagation delays and component mismatches within the transceiver circuit can introduce significant phase offsets between the in-phase and quadrature signals of the local oscillator when measured at a component such as a mixer that receives those signals. FIG. 2 shows an example of in-phase and quadrature signals in which a phase offset has delayed the quadrature signal with respect to the in-phase signal. This is a significant problem for local oscillator signals since a phase offset between the in-phase and quadrature inputs of a mixer will degrade the accuracy of modulation or demodulation performed by the mixer.
A common way of addressing the phase offset problem is to selectively increase the lengths of the transmission lines that carry the local oscillator signals so that phase offsets are compensated by additional path-related delays, and to space out nearby devices. However this increases the routing area of the device, which is contrary to the typical objective of reducing circuit size, and increases power consumption because more power is required for the frequency synthesizer to drive the lengthened transmission lines at high frequencies. Therefore this approach is particularly undesirable in circuits intended for small, portable devices such as wireless LAN transceivers, cell phones, GPS receivers and other similar devices. This approach is also undesirable because the phase shift adjustment is hard wired, and therefore may not provide appropriate compensation for phase offsets that are not predicted during the design stage, such as offsets introduced during layout or fabrication, or offsets that are influenced by the environment in which the circuit is used.
One alternative way of correcting phase offset is through manipulation of the current sources in the frequency divider that produces the signals to adjust the edges of the output signals. While this can improve phase offset, it prevents the use of a resynchronization element at the output of the frequency divider to reduce phase noise generated by the frequency divider.
Another alternative way of addressing the phase offset problem is to use metal-insulator-metal (MiM) capacitors to produce delays in the leading and trailing edges of differential signals.
A first conventional phase offset compensation circuit using MiM capacitors is shown in FIG. 3. In this circuit, each of the differential signal lines 100, 102 may be connected to a voltage source and to ground through MiM capacitors 104, 106, 108, 110. The connections to the voltage source are switched by PMOS transistors 112, 114, and the connections to ground are switched by NMOS capacitors 116, 118. During operation, the PMOS and NMOS transistors are switched at the frequency of the differential signals to shift the positions of the signal transitions. However this circuit has several disadvantages. Signal power is lost because the circuit couples the signal lines to a voltage source or to ground. Also, the effect of coupling the signal lines to the voltage source is not symmetrical with the effect of coupling the signal lines to ground, which distorts the signal waveform and limits the effectiveness of the phase compensation, The switches in the circuit also generate significant switching noise at the power supply.
A second conventional phase offset compensation circuit using MiM capacitors is shown in FIG. 4. In this circuit, a switchable capacitance provided by MiM capacitors 120, 122 and an n-type or p-type MOS transistor 124 is coupled between the differential signal lines 100, 102. The capacitance may be switched into the circuit to create a delay in the differential signals. As shown in FIG. 5, delaying one of the signal pairs produces an offset between the signals that can compensate a pre-existing offset in the signals. However, because MiM capacitors are relatively large, their minimum capacitance is limited, which in turn limits the phase resolution provided by this circuit. Also, the impedance of the transistor 124 may be significantly larger than that of the capacitors 120, 122, and its on resistance is at a maximum during the middle of the transition of the signals. This limits the frequency at which this circuit is effective for providing useful phase offset compensation.